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LTC4240 1 4240f features descriptio u applicatio s u typical applicatio u the ltc ? 4240 is a hot swap tm controller that allows a board to be safely inserted and removed from a live compactpci bus slot. the LTC4240 has a built-in 2-wire i 2 c compatible interface to allow software control and monitoring of device function and power supply status. two external n-channel transistors control the 3.3v and 5v supplies, while two internal switches control the C12v and 12v supplies. electronic circuit breakers protect all four supplies against overcurrent faults. the pwrgd output indicates when all of the supply voltages are within tolerance. the off/on pin is used to cycle the board power or reset the circuit breaker. the i 2 c interface allows the user to turn the device off or on, set resetout, turn on the status led driver and ignore 12v, C12v faults. it also allows the user to read the status of the fault, resetin, resetout, pwrgd, prsnt1# and prsnt2# pins. under a fault condition, the i 2 c interface can also be used to determine which of the four supplies generated the fault. the LTC4240 is available in a 28-pin narrow ssop package. n hot board insertion into compactpci bus n electronic circuit breaker n allows safe board insertion and removal from a live compactpci tm bus n i 2 c tm compatible 2-wire interface n precharge output biases i/o pins during card insertion and extraction n controls 3.3v, 5v, 12v and C12v supplies n foldback current limit with circuit breaker n local_pci_rst# logic on-board n quickswitch ? enable output n status led driver n user programmable supply voltage power-up rate n registers individual supply faults n available in a 28-pin narrow ssop package compactpci hot swap controller with i 2 c compatible interface , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. quickswitch is a registered trademark of quality semiconductor corp. compactpci is a trademark of the pci industrial computer manufacturers group. i 2 c is a trademark of philips electronics n.v. c5 0.01 f c1 0.047 f c4 0.01 f gnd 12v in v eein off/on fault pwrgd resetin 3v in 3v in 5v in 3v sense 3v out 5v in LTC4240 precharge drive 5v out 5v sense gate 12v out v eeout timer resetout early v(i/o) r16 10k r18 1k r17, 1.2k r3 10 5v in r4 10 r15 2k r30 1k r29 10 5v out 5v at 5a 3v out 3.3v at 7.6a 12v out 12v at 500ma v eeout 12v at 100ma 4240 ta01 r11 18 3v in 3v out r6 10k r5 1k r8, 1k r7, 12 c3, 4.7nf r9 24 r1 0.005 q1 si7880dp q2 si7880dp r2 0.007 c2 0.1 f r13 10 r14 10 medium 5v long 5v medium 3.3v long 3.3v long v(i/o) 12v 12v bd_sel# healthy# pci_rst# ground to pci bridge device or equivalent be dgnd led scl sda r19 2.55k 1% r20 1.91k 1% prsnt2# prsnt1# addrin scl sda c8 0.01 f per pin c load (5v out ) c load (3v out ) c load (12v out ) c load (v eeout ) c7 0.01 f per pin c6 0.01 f 5v in z4 z1 z2 z1, z2: smaj12ca z3, z4: ipmt5.0at3 z3 compactpci backplane connector (female) compactpci backplane connector (male) local_pci_rst# r10 100 to quickswitch enable q3 mmbt2222a r12 10k r22, 2.74 r21, 1.74 r25, 1.2k r28, 200 + + + + c9 10nf c10 10nf c11 10nf
LTC4240 2 4240f supply voltages 5v in .................................................................... C0.3v to 12v 12v in ................................................................. C0.3v to 14v v eein ................................................................... 0.3v to C14v input voltages prsnt1#, prsnt2#, scl, resetin, off/on .................................................. C0.3v to 12v 5v out , 5v sense , 3v in , 3v sense , 3v out ............................ C0.3v to (5v in + 0.3v) addrin, precharge ......................... C0.3v to 5v in output voltages timer, fault, pwrgd, sda, resetout, led, drive, gate, 12v out ....................... C0.3v to 14v v eeout ................................................................ C14v to 0.3v be ............................................. 0.3v to (5v in + 0.3v) operating temperature range LTC4240c ............................................... 0 c to 70 c LTC4240i .............................................C40 c to 85 c storage temperature range .................... 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 140 c, q ja = 135 c/w LTC4240cgn LTC4240ign absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 prsnt1# prsnt2# 12v in v eein timer 5v out fault pwrgd be gnd addrin sda scl resetout off/on resetin 12v out v eeout 3v out 3v sense 3v in 5v in 5v sense gate precharge drive dgnd led symbol parameter conditions min typ max units i dd v 12vin supply current off/on = 0v l 38 ma v lko undervoltage lockout 12v in l 7.00 8.00 10.80 v 5v in l 4.10 4.3 4.45 v 3v in l 2.35 2.45 2.55 v v eein l C9 C10.5 v v fb foldback current limit voltage v fb = (v 5vin C v 5vsense ), v 5vout = 0v, timer = 0v l 15 25 35 mv v fb = (v 5vin C v 5vsense ), v 5vout = 3v, timer = 0v l 55 70 85 mv v fb = (v 3vin C v 3vsense ), v 3vout = 0v, timer = 0v l 15 25 35 mv v fb = (v 3vin C v 3vsense ), v 3vout = 2v, timer = 0v l 55 65 80 mv v cb circuit breaker trip voltage v tv = (v 5vin C v 5vsense ), v 5vout = 5v, timer = open l 50 55 60 mv v tv = (v 5vin C v 5vsense ), v 5vout = 0v, timer = open l 61116 mv v tv = (v 3vin C v 3vsense ), v 3vout = 3.3v, timer = open l 50 55 60 mv v tv = (v 3vin C v 3vsense ), v 3vout = 0v, timer = open l 61116 mv t oc overcurrent fault response time (v 5vin C v 5vsense ) = 100mv, timer = open l 25 35 55 m s overcurrent fault response time (v 3vin C v 3vsense ) = 100mv, timer = open l 25 35 55 m s t sc short-circuit response time (v 5vin C v 5vsense ) = 200mv, timer = open l 25 35 55 m s (v 3vin C v 3vsense ) = 200mv, timer = open l 25 35 55 m s i gate(up) gate pin turn-on current off/on = 0v, v gate = 0v, timer = 0v l C 20 C 65 C100 m a i gate(dn) gate pin turn-off current v gate = 5v, (note 3) l 100 200 300 m a i gate(fault) gate pin fault-off current off/on = 0v, v gate = 2v, timer = open, fault = 0v l 2.5 6 8.5 ma d v gate external gate voltage d v gate = (v 12vin C v gate ), i gate = 1 m a l 600 1000 mv the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 12v in = 12v, v eein = C12v, v 3vin = 3.3v, v 5vin = 5v unless otherwise noted.
LTC4240 3 4240f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 12v in = 12v, v eein = C12v, v 3vin = 3.3v, v 5vin = 5v unless otherwise noted. electrical characteristics 5v in C 0.4 symbol parameter conditions min typ max units d v 12v 12v switch voltage drop d v 12v = (v 12vin C v 12vout ), i = 500ma l 300 600 mv d v vee v ee switch voltage drop d v vee = (v eeout C v eein ), i = 100ma l 125 250 mv i cl current foldback 12v in = 12v, 12v out = 0v l C 50 C350 C 800 ma v eein = C12v, v eeout = 0v l 50 250 350 ma i th current fault threshold 12v in = 12v l C550 C 1250 C 1900 ma v eein = C12v l 225 500 800 ma t ts thermal shutdown temperature note 4 150 c v th power good threshold voltage 12v out l 10.8 11.1 11.4 v 5v out l 4.50 4.65 4.75 v 3v out l 2.8 2.9 3.0 v v eeout l C 10 C 10.5 C 10.8 v v il input low voltage off/on, resetin, scl, sda, prsnt1#, prsnt2# l 0.8 v v ih input high voltage off/on, resetin, scl, sda, prsnt1#, prsnt2# l 2v i in input current prsnt1#, prsnt2#, off/on = resetin = sda = scl = 0v, 5v, l 0.08 2 m a off/on, resetin, sda, scl prsnt1#, prsnt2# = 0v, 5v l 0.08 2 m a resetout, fault leakage current resetout = fault = 12v, off/on = 0v, resetin = 3.3v l 0.08 2 m a pwrgd leakage current pwrgd = 12v, off/on = 4v l 0.08 2 m a 5v sense input current 5v sense = 5v, 5v out = 0v, gate = 0v l 55 100 m a 3v sense input current 3v sense = 3.3v, 3v out = 0v, gate = 0v l 55 100 m a 5v in input current 5v in = 5v, timer = 0v, off/on = 0v l 0.8 1.5 ma 3v in input current 3v in = 3.3v, timer = open l 250 600 m a 3v in = 3.3v, timer = 0v l 250 500 m a 5v out input current 5v out = 5v, off/on = 0v, timer = 0v, gate = 0v l 237 400 m a 3v out input current 3v out = 3.3v, off/on = 0v, timer = 0v, gate = 0v l 120 200 m a v eein input current timer = 0v, off/on = 0v l C950 C1200 m a precharge input current v precharge = 1v l 10 m a addrin addrin = 0v, 5v l 0.1 m a i timer timer pin current off/on = 0v, timer = 0v l C6 C 11.5 C17 m a timer = 5v, off/on = 2v l 15 28 55 ma v timer timer threshold voltages l 5 5.5 6.5 v r dis 12v out discharge impedance l 430 1000 w 5v out discharge impedance l 50 100 w 3v out discharge impedance l 150 300 w v eeout discharge impedance l 650 1000 w v oh cmos output high voltage be, i = C100 m a l v v ol cmos output low voltage be, i = 100 m a l 0.4 v output low voltage pwrgd, resetout, fault, sda(i = 3ma) l 0.4 v output low voltage led (i = 10ma) l 0.8 v v pxg precharge reference voltage v 5vin = 5v l 0.9 1 1.1 v i 2 c timing (note 4) f scl scl clock frequency 100 khz t susta start condition setup time 4.7 m s t buf bus free time between stop and start 4.7 m s t hdsta start condition hold time 4 m s
LTC4240 4 4240f symbol parameter conditions min typ max units t sustp stop condition setup time 4 m s t hddat data hold time 300 ns t sudat data setup time 250 ns t low clock low period 4.7 m s t high clock high period 4.0 m s t f clock/data fall time 300 ns t r clock/data rise time 1000 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. 12v in = 12v, v eein = C12v, v 3vin = 3.3v, v 5vin = 5v unless otherwise noted. note 3: off/on pin pulled up to 5v by 1.2k resistor. note 4: parameters guaranteed by design and not tested. electrical characteristics note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. gate pin fault current vs temperature gate pin turn-off current vs temperature gate pin turn-on current vs temperature 12v in supply current vs temperature 3v in supply current vs temperature 5v in supply current vs temperature typical perfor a ce characteristics uw temperature ( c) ?0 gate pin fault current (ma) 8 6 4 2 0 4.0 3.6 3.2 2.8 2.4 25 0 25 50 4240 g01 75 100 temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 12v in supply current (ma) 3v in supply current ( a) 5v in supply current (ma) 4240 g04 gate pin current ( a) ?0 ?0 ?0 ?0 100 4240 g03 gate pin current ( a) 350 300 250 200 150 100 280 260 240 220 1.0 0.9 0.8 0.7 0.6 0.5 4240 g02 4240 g06 4240 g05 v gate = 2v fault = 0v v gate = 5v off/on = 2v v gate = 0v off/on = 0v off/on = 0v off/on = 0v off/on = 0v
LTC4240 5 4240f typical perfor a ce characteristics uw v eein supply current vs temperature 12v in foldback current limit vs temperature v eein foldback current limit vs temperature 12v output current C12v output current 12v out pwrgd threshold voltage vs temperature 3v out pwrgd threshold voltage vs temperature 5v out pwrgd threshold voltage vs temperature v eeout pwrgd threshold voltage vs temperature 0.8 0.9 ?.0 ?.1 ?.2 temperature ( c) 50 25 0 25 50 75 100 v eein supply current (ma) 4240 g07 off/on = 0v 1.6 1.2 0.8 0.4 0 output voltage (v) 02 4 681012 output current (a) 4240 g10 12v in = 12v t a = 25 c 3.00 2.95 2.90 2.85 2.80 temperature ( c) 50 25 0 25 50 75 100 3v out pwrgd threshold voltage (v) 4240 g13 1.6 1.2 0.8 0.4 0 temperature ( c) 50 25 0 25 50 75 100 12v in foldback current limit (a) 4240 g08 12v out = 10v 12v out = 0v temperature ( c) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 4240 g09 ?0 ?5 0 25 50 75 100 temperature ( c) ?0 ?5 0 25 50 75 100 output voltage (v) 0 2 4 6 8 ?0 ?2 output current (a) 0.5 0.4 0.3 0.2 0.1 0 4240 g11 temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 4.75 4.70 4.65 4.60 4.55 4.50 4240 g14 12v out pwrgd threshold voltage (v) 11.4 11.3 11.2 11.1 11.0 10.9 10.8 4240 g12 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 4240 g15 v eeout = ?0v v eeout = 0v v ee foldback current limit (a) v eein = ?2v t a = 25 c 5v out pwrgd threshold voltage (v) v eeout pwrgd threshold voltage (v)
LTC4240 6 4240f 65 60 55 50 45 temperature ( c) 50 25 0 25 50 75 100 3v sense input current ( a) 4240 g16 3v sense = 3.3v temperature ( c) 50 25 0 25 50 75 100 temperature ( c) 50 25 0 25 50 75 100 4240 g17 9.0 8.5 8.0 7.5 7.0 temperature ( c) 50 25 0 25 50 75 100 12v in uvlo threshold voltage (v) 4240 g22 2.55 2.50 2.45 2.40 2.35 temperature ( c) 50 25 0 25 50 75 100 3v in uvlo threshold voltage (v) 4240 g23 4.45 4.40 4.35 4.30 4.25 temperature ( c) 50 25 0 25 50 75 100 5v in uvlo threshold voltage (v) 4240 g24 temperature ( c) ?0 ?5 0 25 50 75 100 temperature ( c) ?0 ?5 0 25 50 75 100 temperature ( c) ?0 ?5 0 25 50 75 100 timer pin current ( a) ?0.0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 4240 g19 timer threshold voltage (v) 6.0 5.8 5.6 5.4 5.2 5.0 4240 g20 circuit breaker response time ( s) 40 38 36 34 32 30 4240 g21 timer pin current (ma) 4240 g18 34 32 30 28 26 24 22 20 18 5v sense = 5v off/on = 0v v timer = 0v off/on = 2v v timer = 5v 65 60 55 50 45 5v sense input current ( a) timer pin floating v in v sense = 0.1v 3v sense input current vs temperature timer pin turn-off current vs temperature timer pin turn-on current vs temperature timer threshold voltage vs temperature 5v/3.3v circuit breaker overcurrent fault response time vs temperature 3v in uvlo threshold voltage vs temperature 5v in uvlo threshold voltage vs temperature 12v in uvlo threshold voltage vs temperature typical perfor a ce characteristics uw 5v sense input current vs temperature
LTC4240 7 4240f temperature ( c) ?0 ?5 0 25 50 75 100 v eein uvlo threshold voltage (v) ?.6 ?.0 ?.4 ?.8 ?.2 ?.6 ?0.0 4240 g25 160 140 120 100 80 temperature ( c) 50 25 0 25 50 75 100 3v out input current ( a) 4240 g33 80 60 40 20 0 temperature ( c) 50 25 0 25 50 75 100 4240 g32 80 60 40 20 0 temperature ( c) 50 25 0 25 50 75 100 3v circuit breaker trip voltage (mv) 5v circuit breaker trip voltage (mv) 5v foldback current limit voltage (mv) 4240 g29 200 160 120 80 40 temperature ( c) 50 25 0 25 50 75 100 v ee internal switch voltage drop (mv) 4240 g27 80 60 40 20 0 temperature ( c) 50 25 0 25 50 75 100 3v foldback current limit voltage (mv) 4240 g28 temperature ( c) ?0 ?5 0 25 50 75 100 4240 g31 temperature ( c) 12v internal switch voltage drop (mv) 500 450 400 350 300 250 200 150 4240 g26 ?0 ?5 0 25 50 75 100 i = 500ma v timer = 0v v timer = open v timer = open i = 100ma 3v out = 0v 3v out = 2v 3v out = 3.3v 3v out = 0v v timer = 0v 5v out = 3v 5v out = 0v 5v out = 5v 5v out = 0v 3v out = 3.3v off/on = 0v 5v out input current ( a) 300 280 260 240 220 200 4240 g34 5v out = 5v off/on = 0v temperature ( c) 50 25 0 25 50 75 100 100 80 60 40 20 0 3v foldback current limit voltage vs temperature 3v circuit breaker trip voltage vs temperature 5v foldback current limit voltage vs temperature 5v circuit breaker trip voltage vs temperature 3v out input current vs temperature v eein uvlo threshold voltage vs temperature 12v in internal switch voltage drop vs temperature v eein internal switch voltage drop vs temperature typical perfor a ce characteristics uw 5v out input current vs temperature
LTC4240 8 4240f pwrgd (pin 8): open-drain power good output. con- nect the cpci healthy# signal to the pwrgd pin. pwrgd remains low while v 12vout 3 11.1v, v 3vout 3 2.9v, v 5vout 3 4.65v and v eeout C10.5v. when any of the supplies drops below its power good threshold volt- age, pwrgd will go high after a 10 m s deglitching time. the switches will not be turned off when pwrgd goes high, unless a fault has occurred. the cpci specification calls for a 0.01 m f bypass capacitor on the backplane for healthy#. be (pin 9): quickswitch bus enable output. the be output remains high until power is good on all supplies. this serves to isolate the i/o data lines during live insertion. this is a cmos output powered by 5v in . gnd (pin 10): analog ground. connect to analog ground plane. addrin (pin 11): i 2 c address programming input. the i 2 c address is programmed by connecting the addrin pin to a resistor divider between the 5v in pin and gnd. see table 1 for 1% resistor values and corresponding ad- dresses. resistors must be placed close to the addrin pin to minimize errors due to stray capacitance and resistance on the board trace. connect this pin to ground if i 2 c is not used. sda (pin 12): i 2 c data input and output. note that ttl levels are used. connect this pin to ground if i 2 c is not used. scl (pin 13): i 2 c clock input, 100khz maximum. note that ttl levels are used. do not float. connect this pin to ground if i 2 c is not used. resetout (pin 14): open-drain reset output. connect the cpci local_pci_rst# signal to the resetout pin. resetout is the logical combination of resetin, pwrgd, and i 2 c resetout latch output. led (pin 15): cpci status led. pulls low to light led when resetout is low or when the i 2 c led latch is set. dgnd (pin 16): digital ground. connect to ground plane. drive (pin 17): external transistors base drive output for bus precharge. connects to the base of an external npn emitter-follower which in turn biases the precharge prsnt1# (pin 1): pci present detect input 1. prsnt1# and prsnt2# are readable over the i 2 c bus. prsnt1# and prsnt2# indicate the maximum power used by the card. do not float. prsnt2# (pin 2): pci present detect input 2. do not float. 12v in (pin 3): 12v supply input. a 0.5 w switch is inter- nally connected between 12v in and 12v out with foldback current limit. an undervoltage lockout circuit prevents the switches from turning on while the 12v in pin is below 8v. 12v in provides power to some of the LTC4240s internal circuitry. see input transient protection section on how to protect 12v in from large voltage transients. v eein (pin 4): C12v supply input. a 1 w internal switch is connected between v eein and v eeout with foldback cur- rent limit. an undervoltage lockout circuit prevents the switches from turning on while v eein is above C 9v. see connecting v eein section for more notes on v eein and v eeout . also refer to input transient protection section. timer/aux 12v in (pin 5): current fault inhibit timing input. connect a capacitor from timer to gnd. with the LTC4240 turned off (off/on = high), the timer pin is internally held at gnd. when the device is turned on, an 11.5 m a pull-up current source is connected to timer. current limit faults will be ignored until the voltage at the timer pin rises above 5.5v. the timer capacitor also serves as an auxiliary charge reservoir for internal v cc in the event the 12v in pin voltage glitches below the LTC4240 uvl threshold voltage. 5v out (pin 6): 5v output sense. the pwrgd pin will not pull low until the 5v out pin voltage exceeds 4.65v. when the power switches are turned off, a 50 w resistor pulls 5v out to ground. fault (pin 7): open-drain fault output . fault is pulled low when a current limit fault is detected. current limit faults are ignored until the voltage at the timer pin is above 5.5v. once the timer cycle is complete, fault pulls low and the LTC4240 turns off (in the event of an overcurrent fault lasting longer than 35 m s). the LTC4240 will remain in the off state until the off/on pin is cycled high then low or power is cycled. note that the off/on cycling can also be performed using i 2 c bus. uu u pi fu ctio s
LTC4240 9 4240f long pin must be connected to 3v in to ensure precharge output. see input transient protection section. 3v sense (pin 23): 3.3v current limit sense. a sense resistor placed between 3v in and 3v sense determines the current limit for this supply. a foldback feature makes the current limit decrease as the voltage at the 3v out pin approaches 0v. to disable current limit, 3v sense and 3v in must be tied together. 3v out (pin 24): 3.3v output sense. the pwrgd pin cannot pull low until the 3v out pin voltage exceeds 2.9v. if no 3.3v input supply is available, tie the 3v out pin to the 5v out pin. when the power switches are turned off, a 150 w resistor pulls 3v out to ground. v eeout (pin 25): C12v supply output. an internal 1 w switch is connected between v eein and v eeout . v eeout must exceed C10.5v before the pwrgd pin pulls low. when the power switches are turned off, a 650 w resistor pulls v eeout to ground. 12v out (pin 26): 12v supply output. a 0.5 w switch is connected between 12v in and 12v out . 12v out must exceed 11.1v before the pwrgd pin can pull low. when the power switches are turned off, a 430 w resistor pulls 12v out to ground. resetin (pin 27): pci reset input. connect the cpci pci_rst# signal to the resetin pin. pulling resetin low will cause resetout to pull low. note that the i 2 c resetin latch output can also set resetout. do not float. off/on (pin 28): off/on input. connect the cpci bd_sel# signal to the off/on pin. when the off/on pin is pulled low, the gate pin is pulled high by a 65 m a current source and the internal 12v and C12v switches are turned on. when the off/on pin is pulled high, the gate pin will be pulled to ground by a 200 m a current source and the 12v and C12v switches turn off. cycling the off/on pin high and low will reset a tripped circuit breaker and start a new power-up sequence. the i 2 c off/on latch output can also be used to reset the electronic circuit breaker. do not float. node. an external 1k resistor between the transistors base and 3v in is needed. precharge (pin 18): precharge monitor input. an inter- nal error amplifier servos the drive pin voltage to keep the precharge node at 1v. becomes valid when long 5v and 3.3v power pins make contact .tie pins 17 and 18 together if precharge function is unused. gate (pin 19): high side gate drive for the external 3.3v and 5v n-channel power transistors. an external series rc network is required for the current limit loop compen- sation and to set the maximum ramp-up rate. during power-up, the slope of the voltage rise at the gate pin is set by the 65 m a current source charging the external gate capacitor or by the 3.3v or 5v current limit and the associated output capacitor. during power-down, a 200 m a current source pulls the gate pin to gnd. the voltage at the gate pin will be modulated to maintain a constant current when either the 3.3v or 5v supply goes into current limit and the timer pin is less than 5.5v. once the timer pin is above 5.5v, and in the event of a current fault condition lasting for longer than 35 m s, the gate pin is immediately pulled to gnd. 5v sense (pin 20): 5v current limit sense. a sense resistor placed between 5v in and 5v sense determines the current limit for this supply. a foldback current feature makes the current limit decrease as the voltage at the 5v out pin approaches 0v. to disable the current limit, 5v sense and 5v in must be tied together. 5v in (pin 21): 5v supply sense input. an undervoltage lockout circuit prevents the switches from turning on when the voltage at the 5v in pin is less than 4.3v. at least one long pin must be connected to 5v in to ensure precharge output. see input transient protection section. 3v in (pin 22): 3.3v supply sense input. an undervoltage lockout circuit prevents the switches from turning on when the voltage at the 3v in pin is less than 2.45v. if no 3.3v input supply is available, connect two series diodes between 5v in and 3v in (tie anode of first diode to 5v in and cathode of second diode to 3v in , figure 15). at least one uu u pi fu ctio s
LTC4240 10 4240f 65mv, timer lo 165mv, timer hi q8 q14 v eein 4 timer 5 v eeout 25 3v out 24 5v out 6 + + q11 q10 200 a 65 a gate 5v out 55mv 12v in 19 5v sense 20 12v in 3 12v out 26 5v in 21 + + + 4.3v uvl ?v uvl 8v uvl + + 3v out 55mv 3v sense 23 3v in 22 resetout 14 1 9 11 13 2 + + + + + 2.45v uvl q6 1v 1.2v 1.2v + 1.2v + 1.2v + led 15 q5 dgnd 16 q3 q2 sda scl addrin prsnt2# prsnt1# be 12 q4 resetin 27 pwrgd 8 q12 fault 7 q13 off/on 28 q7 q9 11.5 a 12v in gnd 10 drive 17 precharge 4240 bd 18 logic q1 cp3 cp2 cp4 a2 a1 cp1 cp6 cp5 a3 v cb v cb 70mv, timer lo 165mv, timer hi block diagra w
LTC4240 11 4240f the LTC4240 is a hot swap controller that allows a board to be safely inserted and removed from a compactpci bus slot. the LTC4240 has built-in 2-wire i 2 c compatible interface hardware to allow software control and monitor- ing of device function and power supply status. hot circuit insertion when a circuit board is inserted into a live compactpci (cpci) backplane slot, supply bypass capacitors on the board can draw huge supply transient currents from the cpci backplane power bus. the transient currents can cause glitches on the power bus, thus causing other boards in the system to reset. the LTC4240 is designed to turn a boards supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live cpci slot without disturbing the system power supplies. the device also protects the supplies from shorts, precharges the bus i/o pins during insertion and extraction and monitors the supply voltages. the LTC4240 includes an i 2 c compatible interface, which allows software control of device func- tions. the LTC4240 is specifically designed for cpci applica- tions where it resides on the plug-in board. for best results, a well bypassed backplane is recommended. LTC4240 feature summary ? allows safe board insertion and removal from a cpci backplane. status led visually identifies when a board is ready for removal. ? controls all four cpci supplies: C12v, 12v, 3.3v and 5v. ? foldback current limit: an analog current limit with a value that depends on the output voltage. if the output is shorted to ground, the current limit drops to keep power dissipation and supply glitches to a minimum. ? 12v and C12v circuit breakers: if either supply remains in current limit for more than 35 m s, the circuit breaker will trip, the supplies will turn off and the fault pin pulls low. ? adjustable 5v and 3.3v circuit breakers: if either supply exceeds current limit for more than 35 m s, the circuit breaker will trip, the supplies will be turned off and the fault pin will be pulled low. in addition, an analog loop will servo the gate pin to limit the current to three times circuit breaker limit during transient conditions. ?i 2 c interface: software control allows user to both write to and read from the device. the user can turn the device off and on, set the status led, set resetout and disable faults on 12v in and v eein . the user can also read the device status: fault, resetin, resetout pwrgd, prsnt1#, prsnt2#, faultcode0 and faultcode1. if a fault occurs, the faultcode bits identify which supply generated the fault. ? current limit during power-up: the supplies are allowed to power-up in current limit. this allows the LTC4240 to power-up boards with widely varying capacitive loads without tripping the circuit breaker. the maximum allowable power-up time is programmable using an external capacitor connected to the timer pin. see timer section ? internal 12v and C12v power switches. ? pwrgd output: indicates the voltage status of the four supply voltages. ? pci_rst# is combined with healthy# and with the i 2 c resetin latch output to create local_pci_rst# output. if healthy# asserts, local_pci_rst# is asserted independent of the other two inputs. ? precharge output: an internal reference and amplifier provide 1v for biasing bus i/o connector pins during cpci card insertion and extraction. ? space saving 28-pin ssop package. i 2 c interface the LTC4240 incorporates an i 2 c compatible 2-wire (clock and data) interface that allows the user to easily query and control the status of the LTC4240. a single analog input pin selects 1 of 32 allowed addresses. the i 2 c bus can be applicatio s i for atio wu uu
LTC4240 12 4240f used to turn off/on the power switches, turn on the status led (alerting the user that its safe to remove the plug-in board), and assert the local_pci_rst# signal. the i 2 c bus is also used to read the logic signals of several device pins: fault, pwrgd, resetin, and resetout. addi- tionally, when a supply generates a current fault, the i 2 c bus can be used to determine which supply generated the fault. see send byte and receive byte sections for a full description of all i 2 c features. the LTC4240 supports send byte and receive byte proto- cols. communication is achieved using the scl and sda pins (ttl compatible input thresholds). the scl pin is the clock input from the i 2 c bus (host) to the LTC4240 (slave). the maximum scl frequency is 100khz. sda is the bidirectional data transfer line between the i 2 c bus and the LTC4240. send byte and receive byte protocols are both comprised of 2 bytes. the first byte for both is the address byte. all communication begins with a start command. programming the i 2 c address the voltage on the addrin pin determines the i 2 c ad- dress. the addrin voltage is set externally with a resistor divider from 5v in to ground (resistor placement must be close to the pin, do not place a bypass capacitor on addrin). this voltage is fed to a 5-bit a/d and compared against the address byte clocked in by the i 2 c bus. the 5- bit a/d allows 32 unique LTC4240 devices to be connected on the same i 2 c bus. 1% resistors should be used to place the voltage at addrin approximately 0.5 lsb away from each code transition. table 1 shows recommended resis- tor values for each of the address code segments. the resistor ratio for each code segment has been optimized for best performance over the specified temperature range. the parallel resistance for the address setting resistors should be kept under 10k. applicatio s i for atio wu uu table 1. suggested addrin 1% resistor values addr recommended allowed addrin r 19(top) r 20(bot) code addrin voltage voltage range resistor resistor 00 0.108125 0.080 to 0.136 8660 191 01 0.264375 0.236 to 0.293 2550 140 02 0.420625 0.393 to 0.449 2550 237 03 0.576875 0.549 to 0.605 2550 332 04 0.733125 0.705 to 0.761 2550 442 05 0.889375 0.861 to 0.918 2550 549 06 1.045625 1.018 to 1.074 3830 1020 07 1.201875 1.174 to 1.230 2550 806 08 1.358125 1.330 to 1.386 2550 953 09 1.514375 1.486 to 1.543 1150 499 10 1.670625 1.643 to 1.699 1020 511 11 1.826875 1.799 to 1.860 8660 4990 12 1.983125 1.955 to 2.021 2550 1690 13 2.139375 2.111 to 2.175 2550 1910 14 2.295625 2.268 to 2.330 1130 1130 15 2.451875 2.424 to 2.488 1370 1330 16 2.608125 2.580 to 2.644 2550 2800 17 2.764375 2.736 to 2.800 2550 3160 18 2.920625 2.888 to 2.950 2550 3570 19 3.076875 3.044 to 3.110 715 1150 20 3.233125 3.200 to 3.262 1150 2100 21 3.389375 3.356 to 3.421 1150 2430 22 3.545625 3.513 to 3.574 1150 2800 23 3.701875 3.669 to 3.731 357 1020 24 3.858125 3.825 to 3.886 2550 8660 25 4.014375 3.981 to 4.041 249 1020 26 4.170625 4.138 to 4.190 1070 5360 27 4.326875 4.294 to 4.349 178 1150 28 4.483125 4.450 to 4.499 133 1150 29 4.639375 4.606 to 4.651 102 1300 30 4.795625 4.763 to 4.805 105 2430 31 4.951875 4.919 to 4.962 100 10000
LTC4240 13 4240f applicatio s i for atio wu uu start and stop commands the start command is defined as a high to low transition of the sda line while the scl line is high. it is an asynchro- nous event issued by the host, waking up all slave devices and alerting them that a slave address is being written onto the bus. only the slave device that matches the address will communicate with the host. the stop command is de- fined as a low to high transition on the sda line while scl is high. it is also an asynchronous event issued by the host to signal the termination of the data transfer. other than start and stop commands, the sda line is allowed to change states only when scl is low. address byte once the LTC4240 has detected a start command, it clocks in the sda line on the succeeding 9 scl rising edges. the first 7 bits clocked in contain the address of the slave device targeted by the host. the first (msb) address bit must be set to low and the second bit must be set to high. the next 5 bits are fed into a digital comparator and compared against the output of an internal 5-bit a/d. if the comparison is true, then there is an address match and the LTC4240 continues to communicate with the host device. the LTC4240 proceeds to acknowledge the address match by pulling the sda line low while scl is low, just before the 9th scl rising edge. figures 1 and 3 show a timing diagram of the start condition and address byte for both the send byte and receive byte protocols. note that the sda bit clocked in with the 8th scl edge determines whether the host is sending or receiving information to/ from the LTC4240. send byte protocol the send byte protocol allows a host to write information into the LTC4240 and command the LTC4240 to perform certain predetermined functions. the host initiates com- munication with a start bit followed by 7 address bits. the address bits are followed by the r/w bit, which is low for send byte. the 9th bit is asserted low by the LTC4240 to acknowledge when there has been an address match. the only time the LTC4240 writes data onto the sda bus during a send byte is to acknowledge the address and command bytes. the first 8 bits are referred to collectively as the address byte. the command byte follows the address byte. the command byte contains the information sent from the host to the LTC4240. after the LTC4240 acknowledges the address byte, each of the next 8 scl rising edges shifts sda from the host into a shift register inside the LTC4240. the first 2 bits clocked into the shift register (2 msbs of the command latch) are not used by the LTC4240. only the 6 lsbs are stored in the command latch on the falling edge of the 8th clock during the command byte. the output of the command latch remains fixed until the next send byte command overwrites it. note that if power is turned off (5v in < 2v), the command and data latches will be cleared. figure 1 shows the timing diagram of the entire send byte protocol. transmission ends when the host issues a stop command. table 2 defines the functions of the 6 command bits. note that some of these functions can override, or can be overridden by, other circuitry and pins of the LTC4240. figure 2 shows the relationship between bits c1 to c3 and other LTC4240 signals. receive byte protocol the receive byte protocol is used by the host to read data from the LTC4240 data latch. this protocol begins with a start command, issued by the host, followed by 7 address bits. the address bits are followed by the r/w bit, which is high for receive byte. the 9th bit is used by the LTC4240 to acknowledge when there is an address match. the data byte then follows the address byte. this byte contains LTC4240 status information. after the LTC4240 acknowledges the address byte, it shifts 8 bits of data onto the sda line. figure 3 shows the entire receive byte timing diagram. note that neither the host or the slave acknowl- edges the data byte (sda line stays high during 9th clock edge of the data byte).
LTC4240 14 4240f applicatio s i for atio wu uu table 2. command byte definitions high low power-up state c7 dont care dont care n/a c6 dont care dont care n/a c5 ignore v eeout faults dont ignore v eeout faults low c4 ignore 12v out faults dont ignore 12v out faults low c3 sets resetout does not set resetout low low c2 turns off/on to off does not set off/on low overrides off/on pin does not override off/on pin c1 turns on led open drain does not turn on led open drain low c0 dont care dont care n/a figure 1. send byte protocol figure 2. send byte command latch and logic scl 12 34 5 67 8 9 12 34 5 678 9 stop sda start ack ack r/wr=0 addr 4 addr 3 addr 2 addr 1 addr 0 c5 c4 c3 c2 c1 xx 01 xx xx latch command byte address byte command byte 4240 f01 4240 f02 c3 is used to set local_pci_rst# (resetout). c2 pulls down the gate of the external n-channel switches. it also turns off the 12v in and v eein internal power switches. c3 c2 c1 resetin pwrgd off/on gate resetout resetout led c1 turns on the external status led independent of resetout.
LTC4240 15 4240f table 3 shows the definition for each data bit. pwrgd, fault, resetin, and resetout external pins can be monitored. prsnt1# and prsnt2# are pci signals that provide information on the power requirements of the board. refer to pci local bus specifications for a detailed description. faultcode1 and faultcode0 are two in- ternal binary encoded signals that, along with fault, indicate which of the four supplies generated a fault. note that the faultcode signals are valid only when fault has been asserted low. see table 4 for description. status led the main function of the led is to alert the user when it is permissible to physically extract the board. the led output of the LTC4240 is an open drain n-channel device capable of sinking 10ma from an externally connected led. this led lights up when resetout (local_pci_rst#) is asserted. upon application of early power, the long 5v pins will power up the LTC4240 and light up the status led. it will remain on until pwrgd (healthy#) is asserted and resetin (pci_rst#) is de- asserted, and the board enters normal operation. note that this led can also be turned on via the i 2 c 2-wire interface. cpci connection pin sequence the staggered length of the cpci male connector pins ensures that all power supplies are physically connected applicatio s i for atio wu uu table 3. status byte definitions s7 logic state of the prsnt2# pin s6 logic state of the prsnt1# pin s5 logic state of the pwrgd pin s4 logic state of the resetout pin s3 logic state of the resetin pin s2 faultcode1 (see table 4) s1 faultcode0 (see table 4) s0 logic state of the fault pin table 4. faultcode encoding description for receive byte faultcode0 faultcode1 fault supply causing fault lo lo lo 3v in lo hi lo 5v in hi lo lo 12v in hi hi lo v eein x x hi none scl 12 34 5 67 8 9 12 34 5 678 9 stop sda start ack ack r/wr=1 addr 4 addr 3 addr 2 addr 1 addr 0 s5 s4 s3 s2 s1 s0 01 s7 s6 address byte data byte 4240 f03 figure 3. receive byte protocol to the LTC4240 before back-end power is allowed to ramp (bd_sel# asserted low). the long pins, which include 5v, 3.3v, v(i/o) and gnd mate first. the short pins, which includes bd_sel# (off/on), mate last. at least one long 5v power pin must be connected to the LTC4240 in order for the precharge voltage to be available during early power. the external components connected to the precharge pin require long 3.3v. the following is a typical hot plug sequence: 1. esd clips make contact. 2. long power and ground pins make contact and early power is established (see early power section). the 1v precharge voltage becomes valid at this stage. power is applied to the pull-up resistors connected to fault, pwrgd and off/on pins. the status led is lit, indicat- ing that the plug-in board is in the process of being connected (local_pci_rst# is asserted). all power switches are off. 3. medium length pins make contact. there are six 5v and eight 3.3v medium length power pins, bringing the 5v total to 8 pins and the 3.3v total to 10 pins. the maximum dc current for the 3.3v and 5v supplies is 10a and 8a, respectively. the i 2 c command latch is initialized to allow seamless cpci hot swap operation. the LTC4240 can be used as a hot swap controller without ever establishing i 2 c communication. both fault and pwrgd continue to be pulled up high at this
LTC4240 16 4240f a high to low transition on bd_sel# causes the voltages on the timer, gate, 3v out , 5v out , 12v out and v eeout pins to begin ramping (see figure 4). the timer pin capacitance is charged by an 11.5 m a current source while the gate capacitance is charged by a 65 m a current source. concurrently, an internal charge pump turns on the gates of the internal power switches that isolate the 12v and C12v supplies. all faults are ignored during the time that the voltage at the timer pin remains below 5.5v. in order to avoid faults due to the charging of the bulk output capacitors, all output voltages must settle before the timer pin reaches 5.5v. see timer section for more details. the 5v out and 3v out supply outputs will ramp up accord- ing to the slowest of the following slew rates: dv dt a c or ii c a or ii c b limit v load v load vout limit v load v load vout = m = = 65 1 1 1 55 5 33 3 , ,() () () () () () () () stage in the hot plug sequence, indicating that the LTC4240 is in reset mode with all power switches off (bd_sel# is still pulled high to long 5v). the 12v and e12v supplies make contact at this stage. zener clamps z1 and z2 plus shunt rc snubbers r13- c4 and r14-c5 help protect the 12v in and v eein pins, respectively, from large transient voltages during hot insertion and short-circuit conditions. the signal pins also connect at this point. this includes the healthy# signal connecting to the pwrgd pin and the pci_rst# signal connecting to the resetin pin. the pwrgd and resetin signals are combined internally with bit 3 (c3) of the i 2 c command latch (see send byte protocol) to generate the local_pci_rst# signal, which is available at the resetout pin. 4. short pins make contact. bd_sel# signal connects to the off/on pin. this starts the electrical part of the connection process. if the bd_sel# signal is grounded on the backplane, then the electrical connection pro- cess starts immediately. note that the electrical con- nection process can be interrupted with the send byte protocol of the i 2 c serial interface. system backplanes that do not ground the bd_sel# signal will instead have circuitry that detects when bd_sel# has made contact with the plug-in board. the backplane logic can then control the power up process by pulling bd_sel# low. figure 4 illustrates the power up sequence. the mating of bd_sel# is represented by the high to low transition of the bd_sel# signal. power-up sequence two external n-channel power mosfets isolate the 3.3v and 5v power paths, while two internal mos switches isolate the 12v and C12v power paths. (see front page application circuit). sense resistors r1 and r2 provide current limit and fault detection for the 3v in and 5v in supplies, while r5 and c1 provide current control loop compensation. current fault detection for the 12v and C12v supplies is done internally. timer 10v/div gate 10v/div 12v out 10v/div v eeout 10v/div 5v out 10v/div 3v out 10v/div lcl_pci_rst# 5v/div bd_sel# 5v/div healthy# 5v/div 10ms/div 4240 f04 figure 4. normal power-up sequence applicatio s i for atio wu u u
LTC4240 17 4240f note that capacitor c1 performs dual functions. in addi- tion to controlling the ramp up rates of the 5v and 3.3v outputs, it also compensates the current limit loop. current limit faults are ignored while the timer voltage is less than 5.5v. once all four supplies are within tolerance, the pwrgd pin (healthy#) will be pulled low and local_pci_reset# (resetout) is free to follow pci_rst#. bit 3 of the i 2 c command latch powers up low, thus not asserting local_pci_rst#. power-down sequence when either bd_sel# (off/on) or bit 2 of the command latch (c2) is set high, a power-down sequence begins (figure 5). the timer pin is immediately pulled low. the gate pin (pin 19) is pulled down by a 200 m a current source to prevent the load currents on the 3.3v and 5v supplies from going to zero instantaneously and glitching the power supply voltages. internal switches are connected to each of the output supply voltage pins to discharge the output bulk capacitors to ground. when any one of the output voltages drops below its pwrgd threshold, the healthy# signal pulls high, local_pci_rst# (resetout) is as- serted low, and the external status led turns on. once the power-down sequence is complete the status led will light up and the cpci card may be removed from the slot. during extraction, the precharge circuit will continue to bias the bus i/o pins at 1v until the long connector pin connections are broken. early power early power usage is restricted by the compactpci (cpci) specification. it is intended to power up the precharge circuit and i/o cells. the cpci specification allows any of the long power pins (5v, 3.3v, v(i/o)) to be used for early power. since early power is not isolated, a resistor should be placed in series with each cpci connector pin. note that if any early power pin is shorted on the inserted card, the current limiting resistor will dissipate the power. in order to maximize the dc current available from the 5v supply, all eight 5v connector pins should be tied together on the inserted card. the same applies to the ten 3.3v cpci connector pins. early power should then be drawn from either or both of the two v(i/o) long pins. if either or both of 5v and 3.3v is used for early power, then the 5v and 3.3v sense resistor values must be chosen such that the 1a/pin cpci rule is not violated. connecting v eein to lessen the likelihood of faulting on power up, the v eeout output pin should be bypassed with a capacitor that is only as large as necessary. a value of 10 m f to 47 m f is recom- mended. if a large value bypass capacitor is used (e.g. 3 100 m f) on v eeout , current limit faults may occur during power-up or during recovery from power failures. timer 10v/div gate 10v/div 12v out 10v/div v eeout 10v/div 5v out 10v/div 3v out 10v/div lcl_pci_rst# 5v/div bd_sel# 5v/div healthy# 5v/div 10ms/div 4240 f05 figure 5. normal power-down sequence applicatio s i for atio wu u u
LTC4240 18 4240f timer 5v/div gate 5v/div 12v out 10v/div v eeout 10v/div 5v out 10v/div 3v out 10v/div bd_sel# 5v/div fault 5v/div 10ms/div 4240 f06 figure 6. power-up into a short on 3.3v output timer during a power-up sequence, an 11.5 m a current source is connected to the timer pin (pin 5) and charges up the external timer pin capacitor. current limit faults are ignored until the timer voltage ramps to 5.5v. this feature allows the LTC4240 to power-up cpci boards with widely varying capacitive loads on the back end supplies. the power-up time for either of the two outputs under current limit conditions is given by the slower of: txv cxv ii or a t gate cxv v a b on out load xvout out limit xvout load xvout on out th () () () () () () () () = = + m 22 1 65 2 where xv out = 5v out or 3v out . the timer period should be set longer than the maximum supply turn-on time but short enough to not exceed the maximum safe operating area of the pass transistor during a short-circuit. v th is the threshold voltage of the external power fet (2v C 3v). the timer period will be: t cv a timer timer = m 55 11 5 . . (3) the timer pin is immediately pulled low when either off/on (pin 28) or bit 2 of command latch (c2) goes high. the timer pin also functions as a temporary auxiliary supply for 12v in . in the event of a large (greater than 1v) glitch on 12v in , the energy stored on the timer capacitor is used as substitute 12v in power. this improves the glitch immunity of the LTC4240. thermal shutdown the internal switches for the 12v and C12v supplies are protected by current limit and thermal shutdown circuits. when the temperature of the die reaches 150 c, all four switches will be latched off and the fault pin (pin 7) will be pulled low. since there is no automatic retry, power will have to be cycled with the off/on pin or the i 2 c command latch. short-circuit protection in order to lower power dissipation in the pass transistors and to mitigate voltage spikes on the supplies during short-circuit conditions, the current limit on each supply is designed to be a function of the output voltage. as the output voltage drops, the current limit decreases. unlike a traditional circuit breaker function where huge currents can flow before the breaker trips, the current foldback feature lowers short-circuit current by at least 50% when powering up into a short. if any supply is in current limit after the timer pin voltage has ramped to 5.5v, then all four pass transistors will be immediately turned off and fault will be asserted low (figure 6). applicatio s i for atio wu u u
LTC4240 19 4240f once the timer voltage has reached 5.5v, all of the supplies will be latched off if any supply enters current limit for at least 35 m s. the 35 m s delay prevents quick current spikesfor example, from a fan turning on from causing false trips of the circuit breaker. during normal operation, the 5v and 3.3v supplies are protected from overcurrent and short-circuit conditions by dual-level circuit breakers. in the event that either supply current exceeds the nominal limit, an internal timer is started. if the supply is still overcurrent after 35 m s, the circuit breaker trips and all the supplies are turned off (figure 7). if a short-circuit occurs on 5v out or 3v out and the supply current exceeds three times the set limit, an analog loop will limit the current to 3 times the value set by r sense and 55mv. if the short persists for more than 35 m s, the LTC4240 latches off (figure 8). it will stay in the latched off state until it is reset using the off/on pin or by using the i 2 c interface. the LTC4240 can also be reset by cycling any of the power supplies. the current limit and the foldback current level for the 5v and 3.3v outputs are both a function of the external sense resistor (r1 for 3v out and r2 for 5v out , see front page). a sense resistor is connected between 5v in (pin 21) and 5v sense (pin 20) for the 5v supply. for the 3.3v supply, a sense resistor is connected between 3v in (pin 22) and 3v sense (pin 23). the current limit and the current foldback current level are given by equations 4 and 5: i mv r i mv r limit xvout sense xvout foldback xvout sense xvout () () () () () () = = 55 4 11 5 where xv out = 5v out or 3v out . equation 4 is the current limit for xv out ? xv in . equation 5 shows the i limit for shorted outputs. both equations assume voltage on timer pin is greater than 5.5v. xv out = 3v out or 5v out . note that since there are only 8 pins connecting 5v in , r sense 3 0.007 w for 5v in . the current limit for the internal 12v switch is set at C1200ma folding back to C350ma and the C12v switch at 500ma folding back to 250ma. selecting r sense an equivalent circuit for the 5v and 3.3v circuit breakers is shown in figure 9. the sense resistor and the circuit breaker threshold voltage determine the fault current that turns off the external fets. sense resistors with a 1% tolerance are recommended. due to part to part and temperature variations for both the sense resistor value and the circuit breaker threshold voltage, the actual cur- rent limit threshold will exhibit some variation. to calcu- late the smallest value of current that will trip the fault comparator, use the largest value of the sense resistor and the smallest value of the threshold voltage. a 0.005 w 1% sense resistor (on the 3.3v supply, for example) with typical temperature coefficients would increase to ap- proximately 0.0051 w (nominal value multiplied by the 1% tolerance and the tc at 70 c). since the minimum value of the threshold voltage is 50mv, this implies a current limit of 9.8a. to arrive at the largest value of the current limit that will turn off the external fets, the nominal value of the applicatio s i for atio wu u u figure 7. overcurrent fault on 5v figure 8. short-circuit fault on 5v gate 5v/div 5v in ?v sense 100mv/div fault 5v/div 20 s/div 4240 f07 gate 5v/div 5v in ?v sense 100mv/div fault 5v/div 20 s/div 4240 f08
LTC4240 20 4240f on resistance the compactpci specification limits the total ir drop of the fet plus the ir drop of the sense resistor to 100mv. for a nominal sense resistor of 0.005 w , if the user limits the 3.3v supply load current to 8.7a, then the maximum fet resistance should be less than 0.0063 w . similarly, for a 6.2a load current on the 5v supply and a 0.007 w sense resistor, the maximum 5v fet resistance should be 0.0088 w . note that above values of fet resistance are worst case over temperature (on the fets datasheet, find the resistance vs temperature curve and de-rate the room temperature maximum value). breakdown voltage the maximum dc voltage that can appear across the drain/source of the external power fet is 5v +10%. during transient events and hot swap conditions, parasitic induc- tances could cause ringing up to 3 times the supply voltage. the use of voltage transient suppressors at the 5v and 3.3v inputs can limit these voltage swings to less than 10v (see front page schematic). similarly, the largest dc voltage that is likely to appear across the gate is 12v +10%. voltage suppressors on the 12v in node will also limit the transient spikes on that node. additionally, the total capacitance on the gate node will serve to filter fast voltage noise spikes. fets with a minimum rating of 20v on both the drain/source and the gate/source are recom- mended. steady state power dissipation for a user selected maximum load current of 8.7a on the 3.3v power supply and a 0.0063 w maximum fet resis- tance, the dc power dissipation is: (i max ) 2 (r dson,max ) = (8.7)(8.7)(0.0063) = 0.477w this is within the soa limits of most power fets. sense resistor drops to 0.0049 w and the largest value of threshold voltage increases to 60mv. this results in a trip current of 12.2a. + + 5v in 5v in r sense 5v sense v cb v cb(max) = 60mv v cb(nom) = 55mv v cb(min) = 50mv 21 20 i load(max) LTC4240* *additional details omitted for clarity 4240 f09 figure 9. circuit breaker equivalent circuit for calculating r sense applicatio s i for atio wu u u plug-in board designers are thus limited to using less than 9.8a when a nominal 0.005 w resistor is used. using more than 9.8a runs the risk of turning off the external fet. since the compactpci specification allows a maximum 1a/pin, at least 10 pins must be used to supply 9.8a. this implies that only the 3.3v supply can use a 0.005 w resistor, since the 5v supply has a maximum of 8 pins available. to adhere to the 1a/pin specification, the 5v sense resistor should be larger than the 3.3v sense resistor. typical applications show a nominal 0.007 w resistor, which results in a 7.04a maximum deliverable current to the plug-in board loads. the 7.04a current implies at least 7 pins on the 5v connector. note that the thermal considerations of the external fet will also place limitations on the maximum allowable current. 5v and 3.3v external fet selection the LTC4240 uses external power fets to limit and modulate the current delivered by the 3.3v and 5v sup- plies. there are several parameters to consider when selecting the fet: 1. on resistance. 2. gate and drain breakdown voltage. 3. steady state and transient power dissipation.
LTC4240 21 4240f transient power dissipation there are certain transient events that can significantly increase the power dissipated by the external fet. if the LTC4240 5v supply (at 5v + 10%) powers up into a 1.5v short (potentially manifested as a short to two diodes in series), then the fet can potentially have 4v across it with 8.8a flowing. this implies a power dissipation of 35.1w. the amount of time the fet will dissipate 35.1w will depend on the relative values of the timer and gate capacitances. for the values specified on the front page application circuit, the gate pin will ramp high signifi- cantly faster than the timer pin, hence transient power dissipation will be set by the timer pin capacitance. the dissipated 35.1w, the ramp time of the timer pin (50ms will be used for this example), and the fet thermal resistance will determine the internal junction tempera- ture of the fet. most fets will specify a maximum internal junction temperature of 150 c. the fet datasheets should have a transient thermal impedance graph. this graph has a family of curves listing the fet transient thermal imped- ance as a function of duty cycle. the duty cycle refers to what percentage of the time the fet is in the short circuit condition. if we choose the si7880dp fet and assume that the board on which the fet is placed has minimal heat sinking capability, and further assume that the user will turn on the board every 2.5 seconds (0.02 duty cycle: 50ms on, 2450ms off), then by looking at the junction-to- ambient curve we note that with a 70 c ambient tempera- ture, the si7880dp internal junction temperature will be 172 c. this is above the absolute maximum rating of the fet, and although operating at this temperature will not damage the fet immediately, it does affect its long term reliability. conversely, if we assume that there is a perfect heat sink for the si7880dp package, then we would use the junction-to-case curve and calculate a value of 117 c with a 70 c ambient temperature. the si7880dp comes in a thermally enhanced package whose drain lead is a large piece of metal that can conduct heat away from the internal junction of the fet. to achieve best performance, the drain of the si7880dp should be connected to a piece of copper (as large as possible) on the board. note that if the output is shorted to ground, the current foldback feature will cut the power dissipation by at least a factor of two. applicatio s i for atio wu u u when the LTC4240 is turned on and the large 5v out output capacitor (2000 m f or more) is charged, it is pos- sible that the 5v fet will dissipate as much as the 35.1w described above. if there is no dc load at 5v out , then 8.8a will charge the 2000 m f in less than 2ms, which should not pose any thermal problems for the si7880dp. if the dc load at 5v out approaches the current limit, then the above analysis should be used to calculate the internal junction temperature of the fet. output voltage monitor the dc level of all four supply outputs is monitored by the power good circuitry. when any of the four supply outputs falls below its specified level (see dc electrical specifica- tions) for longer than 10 m s, the pwrgd (healthy#) open drain pin will be deasserted and the local_pci_rst# signal will be asserted low. this does not generate a fault condition. the local_pci_rst# signal (resetout pin) is derived from the healthy# (pwrgd pin), pci_rst# (resetin pin), and bit 3 of the command latch (see table 5). table 5. local_pci_rst# truth table bit 3 (c3 ) pci_rst# healthy# command latch local_pci_rst# lo x x lo xhix lo x x hi lo hi lo lo hi precharge the precharge input and drive output pins are used to generate the 1v precharge voltage that biases the bus i/o connector pins during board insertion and extraction (figure 10). the LTC4240 is capable of generating precharge voltages other than 1v. figure 11 shows a circuit that can be used in applications requiring a precharge voltage less than 1v. the circuit in figure 12 can be used for applications that need precharge voltages greater than 1v. table 6 lists suggested resistor values for r11a and r11b vs precharge voltage for the application circuits shown in figures 11 and 12.
LTC4240 22 4240f table 6. r1 and r2 resistor values vs precharge voltages v precharge r11a r11b v precharge r11a r11b 1.5v 18 w 9.09 w 0.9v 16.2 w 1.78 w 1.4v 18 w 7.15 w 0.8v 14.7 w 3.65 w 1.3v 18 w 5.36 w 0.7v 12.1 w 5.11 w 1.2v 18 w 3.65 w 0.6v 11 w 7.15 w 1.1v 18 w 1.78 w 0.5v 9.09 w 9.09 w 1v 18 w 0 w figure 12. precharge voltage greater than 1v figure 11. precharge voltage less than 1v 3v in 5v in 3v in 5v in 22 21 LTC4240* 4240 f10 r i01 10 , 5% i/o i/o r i0128 10 , 5% pci bridge (21154) up to 128 i/o lines data bus 3v in gnd precharge 18 drive 17 10 r pre1 10k 5% precharge out 1v 20% i out = 55ma r11 18 , 5% r pre128 10k 5% r8 1k, 5% r7 12 , 5% c3 4.7nf r9 24 , 5% compactpci backplane connector (female) compactpci backplane connector (male) medium 5v long 5v 3.3v long 3.3v ground i/o pin 1 i/o pin 128 ? ? ? ? ? ? ? ? r22 2.74 r21 1.74 *additional details omitted for clarity q3 mmbt2222a q3 mmbt2222a c3 4.7nf r7 12 , 5% r9 24 , 5% r8 1k, 5% 3v in precharge out gnd precharge drive LTC4240* 10 18 17 r11a r11b v precharge = ?1v r11a r11a + r11b 4240 f11 *additional details omitted for clarity q3 mmbt2222a c3 4.7nf r7 12 , 5% r9 24 , 5% r8 1k, 5% 3v in precharge out gnd precharge drive LTC4240* 10 18 17 r11a r11b v precharge = ?1v r11a + r11b r11a 4240 f12 *additional details omitted for clarity figure 10. precharge application circuit precharge resistors are used to connect the 1v bias voltage to the compactpci connector i/o lines. this allows live insertion of the i/o lines with minimal disturbance. figure 13 shows the precharge application circuit for 5v signaling environments. the precharge resistor require- ments are more stringent for 3.3v and universal hot swap signaling. if the total leakage current on the i/o line is less applicatio s i for atio wu u u
LTC4240 23 4240f applicatio s i for atio wu u u than 2 m a, then a 50k resistor can be connected directly from the 1v bias voltage to the i/o line. however, many ics connected to the i/o lines can have leakage currents up to 10 m a. for these applications, a 10k resistor is used but must be disconnected when the board has been seated as determined by the state of the bd_sel# signal. figure 14 shows a precharge circuit that uses a bus switch to gnd 5v in off/on 5v in LTC4240* precharge drive 21 28 18 17 z4: 1pmt5.0at3 *additional details omitted for clarity data bus i/o 4240 f14 q3 mmbt2222a 10 r11 18 , 5% r18 1k, 5% 3v in r i01 10 5% r pre1 10k 5% r pre128 10k 5% precharge out 1v 10% i out = 55ma i/o r i0128 10 5% r22 2.74 r8 1k, 5% r7 12 , 5% c3, 4.7nf r9 24 pci bridge chip medium 5v long 5v bd_sel# ground i/o pin 1 i/o pin 128 ? ? ? ? ? ? z4 up to 128 i/o lines 0.1 f 100 long 5v q4 mmbt3906 r26 51.1k, 5% r27 75k 5% bus switch v dd oe out out in compactpci backplane connector (female) compactpci backplane connector (male) r17 1.2k 5% figure 14. precharge bus switch application circuit for 3.3v and universal hot swap boards figure 13.precharge application circuit for 5v signaling systems gnd 5v in off/on 5v in LTC4240* precharge drive 21 28 18 17 z4: 1pmt5.0at3 *additional details omitted for clarity data bus i/o 4240 f13 precharge out 1v 10% i out = 55ma r pre1 10k 5% r11 18 , 5% r18 1k, 5% 3v in r i01 10 5% i/o r i0128 10 5% r17 1.2k 5% r22 2.74 r pre128 10k 5% r8 1k, 5% r7 12 , 5% c3, 4.7nf r9 24 pci bridge chip medium 5v long 5v bd_sel# ground i/o pin 1 i/o pin 128 ? ? ? ? ? ? long 5v z4 up to 128 i/o lines q3 mmbt2222a compactpci backplane connector (female) compactpci backplane connector (male) connect the individual 10k precharge resistors to the LTC4240 1v precharge pin. the electrical connection is made (bus switches close) when the voltage on the bd_sel# pin of the plug-in card is above 4.4v, which occurs just after the long pins have made contact. the bus switches are subsequently electrically disconnected when the board connector makes contact with the bd_sel# pin (bus switch oe pin is pulled high by q4).
LTC4240 24 4240f prsnt1# prsnt2# expansion configuration open open no plug in board present ground 10k pull-up plug-in board present, maximum power consumption 10k pull-up ground plug-in board present, nominal power consumption ground ground plug-in board present, minimum power consumption other compactpci applications if no 3.3v supply input is required, figure 15 illustrates how the LTC4240 should be configured. for applications where the bd_sel# connector pin is grounded on the backplane, the circuit in figure 16 allows the LTC4240 to be reset simply by pressing a pushbutton switch on the cpci plug-in board. this arrangement allows for manual resetting of the LTC4240s circuit break- ers. input transient protection hot-plugging a board into a backplane generates inrush currents from the backplane power supplies. this is due to the charging of the plug-in board bulk capacitance. to reduce this transient current to a safe level, the cpci hot swap specification restricts the amount of unswitched capacitance used on the input side of the plug-in board. each pin connected to the cpci female connector on the plug-in board is allowed at most 0.01 m f/pin. bulk capaci- tors are only allowed on the switched output side of the LTC4240 (5v out , 3v out , 12v out , v eeout ). some bulk capacitance is allowed on the early power planes, but only because a current limiting resistor is assumed to separate the connector from the bulk capacitor. circuits normally placed on the unswitched early power (pci bridge, for example) need to have a current limiting resistor. applicatio s i for atio wu u u the assumption by the compactpci specification is that there is a diode to 3.3v on the circuit that is driving the bd_sel# pin. the 1.2k resistor pull up to 5v in on the plug- in card will thus be clamped by the diode to 3.3v. if the bd_sel# pin is being driven high, the actual voltage on the pin will be approximately 3.9v. this is still above the high ttl threshold of the LTC4240 off/on pin, but low enough for q4 to disable the bus switches and thus remove the 10k resistors from the i/o lines. note that bd_sel# is ordi- narily connected to v(i/o), which in turn is allowed to be driven by either 3.3v or 5v. for applications such as shown in figure 14, the pull up on bd_sel# is restricted to the long 5v pins. a bus switch with no internal diode to v dd is preferred. since the power to the bus switch is derived from one of the unswitched power planes, a 100 w resistor plus a 0.1 m f bypass capacitor should be placed in series with its power supply. when the plug-in card is removed from the connector, the bd_sel# connection is broken first, and the bd_sel# voltage pulls up to 5v. this causes q4 to turn off, which re- enables the bus switch, and the precharge resistors are again connected to the LTC4240 precharge pin for the remainder of the board extraction process. the LTC4240 be pin can alternatively be used to drive the enable input of the bus switch. the be signal would then keep the i/o lines precharged until all supplies reached power good status. the resistor in series with the precharge pin protects the internal circuitry from large voltage transients during live insertion. prsnt1#, prsnt2# prsnt1# and prsnt2# are pci signals that convey the plug-in boards power consumption information. these pins should either be shorted to ground or be connected to early power with a 10k resistor. the voltage levels (ttl) at the prsnt#1, 2 pins can be read using the i 2 c 2-wire interface.
LTC4240 25 4240f disallowing bulk capacitors on the input power pins mitigates the inrush current during hot plug. however, it also tends to create a resonant circuit formed by the inductance of the backplane power supply trace and the parasitic capacitance of the plug-in board (mainly due to the large power fet). upon board insertion, the ringing of this circuit will exhibit peak overshoot as high as 2.5 times the steady state voltage (>30v for 12v). there are two methods for abating the effects of these high voltage transients: using zener clamps, and using snubber applicatio s i for atio wu u u figure 17. place transient protection device close to the LTC4240 c1 0.047 f c7 0.1 f 0.1 f 3v in medium 3.3v medium 5v 3v sense 22 3v out 24 5v in 21 5v out 6 5v sense 20 23 gate 19 r3 10 r4 10 5v out at 5a 3v out at 7.6a r5 1k r1 0.005 q1 si7880dp q2 si7880dp r2 0.007 z3 z4 LTC4240* 1644 f17 gnd 10 z3, z4: 1pmt5.0at3 *additional details omitted for clarity long 5v long 3.3v 2.7 r23 2.7 r22, 2.74 r21, 1.74 figure 15. 5v supply only application circuit medium 5v long 5v c1 0.047 f gnd 21 3v out 6 LTC4240* 22 5v out 24 23 20 gate 19 10 4240 f15 r5 1k r22 2.74 compactpci backplane connector (female) compactpci backplane connector (male) gnd 5v in 5v in d1 5v sense 3v in 3v sense r4 10 5v out r2 0.007 q2 si7880dp d2 d1, d2: bav99 c l(5vout) z4 *additional details omitted for clarity z4: 1pmt5.0at3 gnd LTC4240* 10 1.2k pushbutton switich 100 v(i/o) 1k gnd off/on 28 bd_sel# 4240 f16 *additional details omitted for clarity compactpci backplane connector (female) compactpci backplane connector (male) figure 16. bd_sel# pushbutton toggle switch networks. snubbers are rc networks whose time constants are large enough to damp the inductance of the parasitic resonant circuit. the snubber capacitor should be 10x to 100x the value of the plug-in board parasitic capacitance. the value of the series snubber resistor should be large enough to damp the resulting r-l-c circuit and is typically between 1 w and 50 w . these protection networks should be mounted very close to the LTC4240 in order to minimize parasitic inductance. this is shown in figure 17 for the 3.3v and 5v supplies.
LTC4240 26 4240f current flow to source *additional details omitted for clarity. drawing is not to scale! 4240 f18 track width w: 0.03" per ampere on 1oz cu foil d d d d g s s s current flow to load current flow to load sense resistor via to gnd plane gnd gnd 5v out 5v 5v in 5v via/path to gnd gate r4 r5 c1 c timer w w w power mosfet LTC4240cgn* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 similar layout for 3.3v rail not shown note (see front page schematic) that the 12v and C12v show 0.01 m f snubber capacitors. this is consistent with the cpci specification since we also recommend a 10 w snubber resistor. the 12v in pin is the most sensitive to high energy large voltage transients. a transient voltage suppressor with a breakdown voltage between 13.2v and 15v is advisable. the tvs should also be able to dissipate at least 150w. the smaj12ca can be used for both 12v in and v eein . place the tvs close to the LTC4240. see front page schematic. figure 18. recommended layout for power mosfet, sense resistor and gate components for the 5v rail. similar layout for 3.3v rail not shown applicatio s i for atio wu u u pcb layout considerations for proper operation of the LTC4240s circuit breaker function, a 4-wire kelvin connection to the sense resistors is highly recommended. a recommended pcb layout for the sense resistor, the power mosfet, and the gate drive components around the LTC4240 is illustrated in figure 18. the drawing is not to scale and is only intended to show the low resistance, external high current path. in hot swap applications where load currents can reach 10a, narrow pcb tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. since the sheet resistance of 1 ounce copper is approximately 0.5m w /square, track resistances add up quickly in high- current applications. thus, to keep pcb track resistance and temperature rise to a minimum, the suggested trace width in these applications for 1 ounce copper is 0.03" for each ampere of dc current. in order to help dissipate the heat generated by the power mosfet, the copper trace connected to the drain should be made as large as possible. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the pc board. for 1 ounce copper plating, a general rule is 1a of dc current per via, making sure the via is properly dimensioned so that solder completely fills any void. for other plating thicknesses, check with your pcb fabrication facility. power mosfet and sense resistor selection table 7 lists some current mosfet transistors that are available. table 8 lists some current sense resistors that can be used with the LTC4240s circuit breakers. table 9 lists supplier web site addresses for discrete components mentioned throughout the LTC4240 data sheet. high current applications should select a mosfet with very low on-resistance and good transient thermal character- istics.
LTC4240 27 4240f table 7. n-channel power mosfet selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8 on semiconductor r ds(on) = 0.1 w 2 to 5 mmsf5n02hd single n-channel so-8 on semiconductor r ds(on) = 0.025 w 5 to 10 mtb50n06v single n-channel dd-pak on semiconductor r ds(on) = 0.028 w 5 to 10 irf7457 single n-channel so-8 international rectifier r ds(on) = 0.007 w 5 to 10 si7880dp single n-channel powerpak tm vishay-siliconix r ds(on) = 0.003 w table 8. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r055f 0.055 w , 0.5w, 1% resistor irc-tt wsl1206r055 vishay-dale 2a lr120601r028f 0.028 w , 0.5w, 1% resistor irc-tt wsl1206r028 vishay-dale 5a lr120601r011f 0.011 w , 0.5w, 1% resistor irc-tt wsl2010r011 vishay-dale 7.9a wsl2512r007 0.007 w , 1w, 1% resistor vishay-dale 11a wsl2512r005 0.005 w , 1w, 1% resistor vishay-dale powerpak is a trademark of vishay-siliconix applicatio s i for atio wu u u table 9. manufacturers web site manufacturer web site international rectifier www.irf.com on semiconductor www.onsemi.com irc-tt www.irctt.com vishay-dale www.vishay.com vishay-siliconix www.vishay.com diodes, inc. www.diodes.com information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4240 28 4240f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1421 hot swap controller dual supplies for 3v to 12v, additionally C12v ltc1422 hot swap controller in so-8 single supply from 3v to 12v lt1641-1/lt1641-2 positive voltage hot swap controller in so-8 supplies from 9v to 80v, latched off/auto retry ltc1642 fault protected hot swap controller 3v to 15v, overvoltage protection up to 33v ltc1643al/ltc1643al-1/ pci bus hot swap controllers 3.3v, 5v, 12v, C12v supplies for pci bus ltc1643ah ltc1644 compactpci hot swap controller 3.3v, 5v, 12v, i/o precharge and local reset logic ltc1645 2-channel hot swap controller operates from 1.2v to 12v, power sequencing ltc1646 compactpci hot swap controller for 3.3v and 5v 3.3v and 5v only, i/o precharge and local reset logic ltc1647 dual hot swap controller dual on pins for supplies from 3v to 15v ltc4211 single hot swap controller with multifunction current control 2.5v to 16.5v, dual level circuit breaker, no gate capacito r ltc4230 triple hot swap controller with multifunction current control 1.7v to 16.5v, dual level circuit breaker, no gate capacito r ltc4241 pci hot swap controller with 3.3v auxiliary 3.3v, 5v, 12v and 3.3vaux supplies for pci bus lt4250l/lt4250h C48 hot swap controllers in so-8 active current limiting, supplies from C20v to C80v ltc4251 C48 hot swap controller in sot-23 floating topology, active current limiting ltc4252 C48 hot swap controller in msop floating topology, active current limiting, pwrgd output ltc4350 hot swappable load share controller eliminates oring diodes, identifies and localizes faults package descriptio u gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) ? linear technology corporation 2003 lt/tp 0403 2k ? printed in usa .386 ?.393* (9.804 ?9.982) gn28 (ssop) 0502 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.191 ?0.249) .053 ?.069 (1.351 ?1.748) .008 ?.012 (0.203 ?0.305) .004 ?.009 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale

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